DSpace Collection:

A Permanental Analog of the Rank-Nullity Theorem for Symmetric Matrices

2026-01-01T00:00:00Z

Title: A Permanental Analog of the Rank-Nullity Theorem for Symmetric Matrices Authors: Pant, Priyanshu; Singh, Ranveer Abstract: The rank of an n × n matrix A is equal to the maximum order of a square submatrix with a nonzero determinant; it can be computed in O(n2.37) time. Analogously, the maximum order of a square submatrix with nonzero permanent is defined as the permanental rank ρper(A). Computing the permanent or the coefficients of the permanental polynomial per(xI − A) is #P-complete. The permanental nullity ηper(A) is defined as the multiplicity of zero as a root of the permanental polynomial. We establish a permanental analog of the rank-nullity theorem, ρper(A) + ηper(A) = n for symmetric nonnegative matrices, positive semidefinite matrices, and adjacency matrices of balanced signed graphs. Using this theorem, we can compute the permanental nullity for these classes in polynomial time. For {0, ±1}-matrices, we also provide a complete characterization of when the permanental rank-nullity identity holds. © Priyanshu Pant, Surabhi Chakrabartty, and Ranveer Singh.

Approx-Ch: An Approximate Chameleon Clustering for Large-Scale and High-Dimensional Data

2025-01-01T00:00:00Z

Title: Approx-Ch: An Approximate Chameleon Clustering for Large-Scale and High-Dimensional Data Authors: Singh, Priyanshu; Ahuja, Kapil Abstract: Hierarchical clustering remains a fundamental challenge in data mining, particularly when dealing with real-world datasets. Here, traditional approaches fail to scale effectively when the datasets are large-scale and high-dimensional. Recent Chameleon clustering algorithms - Chameleon2, M-Chameleon, and INNGS-Chameleon - have proposed advanced strategies that try to address this challenge. However, they still suffer from O(n2) computational complexity. We address this challenge here by introducing Approximate-Chameleon (Approx-Ch) that has O(n log n) complexity.Our algorithm has three parts. First, Graph Generation - here we use approximate k-NN search instead of an exact one, as used by earlier three algorithms. This results in fast nearest-neighbor computation, significantly reducing the graph generation time. Second, Graph Partitioning - here we use a multi-level partitioning approach as compared to a single-level one, mostly used by the prior three works. This change ensures that graph partitioning is robust to the errors introduced by approximate graph generation. This also facilitates minimal configuration requirements. Third, Merging - here we follow Chameleon2 by retaining its flood-fill heuristic and its merging criteria since it is the cheapest among the earlier three algorithms.On real-world benchmark datasets used in former three works, Approx-Ch delivers an average improvement of 5% in clustering quality and reduces total run-time by 86%. This demonstrates that algorithmic efficiency and clustering quality can co-exist in large-scale hierarchical clustering. © 2025 IEEE.

Synchrophasor Data Anomaly Detection Using Unsupervised Transformer Autoencoder

2025-01-01T00:00:00Z

Title: Synchrophasor Data Anomaly Detection Using Unsupervised Transformer Autoencoder Authors: Kukadiya, Purna; Jain, Trapti; Hubballi, Neminath Abstract: Detecting anomalies in synchrophasor measurement data is critical for improving situational awareness and supporting better decision-making in power grid operations and control, especially as cyber-physical threats continue to grow. This work proposes an unsupervised Transformer Autoencoder (TAE) for anomaly detection in Phasor Measurement Unit (PMU) data with spatio-temporal characteristics. The model leverages a self-attention mechanism to capture complex temporal dependencies and integrates an autoencoder structure for unsupervised learning. Unlike conventional autoencoder-based methods that require entirely clean training data, the proposed TAE can be trained on datasets containing mostly normal measurements with a small fraction of anomalies, making it more practical for real-world applications. In addition, a block-wise Z-score normalization scheme with moving window is introduced to improve robustness, enabling the model to better identify spatio-temporal variations in PMU data. The model is validated using a high-resolution PMU dataset generated from a cyber-power testbed that includes a wide range of realistic cyber and physical anomalies. Extensive experiments show that the proposed TAE delivers consistent accuracy and strong generalization across different thresholds and window sizes when applied to realistic datasets. Results indicate performance of the proposed TAE algorithm with precision, recall and F1-Score of 97.20%, 98.58%, and 97.89%, respectively. © 2025 IEEE.

SHiELD: Functional Obfuscation of DSP Cores Using HLS Based One-Way Random Function and Reconfigurable Composite Switching Obfuscation Cells

2026-01-01T00:00:00Z

Title: SHiELD: Functional Obfuscation of DSP Cores Using HLS Based One-Way Random Function and Reconfigurable Composite Switching Obfuscation Cells Authors: Sengupta, Anirban; Anshul, Aditya; Bhui, Nabendu Abstract: Successful reverse engineering (RE) of digital signal processing (DSP) integrated circuits (ICs) by an attacker provides him/her a chance to pirate the DSP-based intellectual property (IP) and insert malicious logic. It is thus central to devise low-cost sturdy functional obfuscation techniques for DSP cores that hinders RE attempt (or increases attackers effort manifold). There has been meager effort on devising robust high-level synthesis (HLS) based functional obfuscation methodology that is low-cost/power. This paper presents a novel Secure High-Level synthesis based functional obfuscation methodology for Enhanced security of DSP cores called “SHiELD” that is driven through HLS based one-way random (OWR) function and reconfigurable composite switching obfuscation (CSO) cells, integrated with design space exploration process. The proposed approach offers security against different relevant attacks and in overall effectively thwarts RE attempt with the aid of proposed multi-key bit CSO cells, and custom OWR function. The results of the proposed approach in comparison with prior approaches yielded several magnitudes of higher security (robust obfuscation strength and lower probability of key retrieval) upto ∼10154 (for FIR-2 benchmark calculated using Equation (1)), lower power (of ∼10.6%) and reduction in design cost (of 0.91%). © 2026 Copyright held by the owner/author(s).