https://dspace.iiti.ac.in:8080/jspui/handle/123456789/13907 Tue, 12 May 2026 17:10:18 GMT 2026-05-12T17:10:18Z https://dspace.iiti.ac.in:8080/jspui/handle/123456789/17093 Title: A Novel Federated Learning Framework for IoMT Security Using Integrated Fingerprinting Authors: Satapathy, Jyoti Ranjan Abstract: The Internet of Military Things (IoMT) demands robust and secure communication for mission-critical operations. However, traditional cryptographic methods often fall short due to scalability challenges and the resource constraints of IoT devices. To overcome these limitations, we propose a Federated Learning (FL) framework for RF fingerprinting, which utilizes the unique hardware characteristics of devices for authentication, eliminating the need for resource-intensive cryptographic techniques. By enabling distributed learning across devices, FL enhances privacy by minimizing centralized data storage while supporting real-time, continuous authentication. This innovative approach effectively counters spoofing and impersonation attacks, ensuring that only authorized devices can communicate. Simulation results demonstrate that the framework is both scalable and resource-efficient, delivering high authentication accuracy and making it an optimal solution for securing IoMT in dynamic military environments. © 2025 Elsevier B.V., All rights reserved. Wed, 01 Jan 2025 00:00:00 GMT https://dspace.iiti.ac.in:8080/jspui/handle/123456789/17093 2025-01-01T00:00:00Z https://dspace.iiti.ac.in:8080/jspui/handle/123456789/16304 Title: Privacy-Preserving Authentication for IoMT: A Federated Learning Approach Leveraging RF Fingerprinting Authors: Satapathy, Jyoti Ranjan Abstract: The Internet of Military Things (IoMT) requires secure, reliable communication to support critical operations, but traditional cryptographic methods often struggle with scalability and place significant demands on IoT device resources. To overcome these limitations, we present a Federated Learning (FL) framework for RF fingerprinting that uses distinct hardware characteristics for device authentication, minimizing the need for heavy cryptographic processes. FL facilitates distributed learning across devices, enhancing privacy by reducing data centralization and enabling continuous, real-time authentication. This framework effectively protects against spoofing and impersonation attacks, ensuring secure communication among authorized devices. Simulations demonstrate that the approach is scalable, resource-efficient, and achieves high authentication accuracy, making it ideally suited for securing IoMT in complex military environments. © 2025 IEEE. Wed, 01 Jan 2025 00:00:00 GMT https://dspace.iiti.ac.in:8080/jspui/handle/123456789/16304 2025-01-01T00:00:00Z https://dspace.iiti.ac.in:8080/jspui/handle/123456789/15982 Title: MAC-DNN: An Optimized Hardware Implementation of MAC Unit in Neuron Engine for Deep Neural Network Applications Authors: Verma, Rajesh; Vishwakarma, Santosh Kumar Abstract: Object detection and analysis using deep neural networks (DNNs) have become significant challenges due to their computational and power requirements. Hence, such computation is possible on general-purpose platforms like central processing units (CPUs), graphic processing units (GPUs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs). However, the development of high computational platforms is a critical challenge for efficient edge computing tasks like object detection, where power and bandwidth are low but faster and energy-efficient solutions are required. System-on-chip (SoC) designs are an optimistic solution for addressing these challenges. This study presents the power and delay-optimized Multiply-Accumulate (MAC) unit architecture for DNN and compares the parameters of 4-bit, 8-bit, 12-bit, and 16-bit MAC units. Vivado software has been employed to construct the MAC unit. It can carry out addition, accumulation, and multiplication operations. The design is analyzed and simulated using the Vivado High-Level Synthesis (HLS) tool, which is subsequently deployed on the Zybo Evaluation and Development Kit. The proposed approach outperforms the existing state-of-the-art models in terms of processing time and power for different precisions. © 2025 IETE. Wed, 01 Jan 2025 00:00:00 GMT https://dspace.iiti.ac.in:8080/jspui/handle/123456789/15982 2025-01-01T00:00:00Z https://dspace.iiti.ac.in:8080/jspui/handle/123456789/15624 Title: MAC-DNN: An Optimized Hardware Implementation of MAC Unit in Neuron Engine for Deep Neural Network Applications Authors: Verma, Rajesh; Vishwakarma, Santosh Kumar Abstract: Object detection and analysis using deep neural networks (DNNs) have become significant challenges due to their computational and power requirements. Hence, such computation is possible on general-purpose platforms like central processing units (CPUs), graphic processing units (GPUs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs). However, the development of high computational platforms is a critical challenge for efficient edge computing tasks like object detection, where power and bandwidth are low but faster and energy-efficient solutions are required. System-on-chip (SoC) designs are an optimistic solution for addressing these challenges. This study presents the power and delay-optimized Multiply-Accumulate (MAC) unit architecture for DNN and compares the parameters of 4-bit, 8-bit, 12-bit, and 16-bit MAC units. Vivado software has been employed to construct the MAC unit. It can carry out addition, accumulation, and multiplication operations. The design is analyzed and simulated using the Vivado High-Level Synthesis (HLS) tool, which is subsequently deployed on the Zybo Evaluation and Development Kit. The proposed approach outperforms the existing state-of-the-art models in terms of processing time and power for different precisions. © 2025 IETE. Wed, 01 Jan 2025 00:00:00 GMT https://dspace.iiti.ac.in:8080/jspui/handle/123456789/15624 2025-01-01T00:00:00Z