1. IDR@IIT Indore

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Results 1-10 of 213 (Search time: 0.001 seconds).
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Issue DateTitleAuthor(s)
2017Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesisRoy, Dipanjan; Sengupta, Anirban
2023Methodology for exploration of security-design cost trade-off for signature-based security algorithmsSengupta, Anirban; Chaurasia, Rahul
2022IP Core Protection of Image Processing Filters with Multi-Level Encryption and Covert Steganographic Security ConstraintsAnshul, Aditya; Sengupta, Anirban
2015Design space exploration of datapath (architecture) in high-level synthesis for computation intensive applicationsSengupta, Anirban
2013D-logic exploration: Rapid search of Pareto fronts during architectural synthesis of custom processorsSengupta, Anirban; Mishra, Vipul Kumar
2017DSP design protection in CE through algorithmic transformation based structural obfuscationSengupta, Anirban; Roy, Dipanjan
2020Design Space Exploration of DSP Hardware Using Adaptive PSO and Bacterial Foraging for Power/Area-Delay Trade-OffSengupta, Anirban; Rathor, Mahendra
2018Comprehensive operation chaining based schedule delay estimation during high level synthesisMishra, Vipul Kumar; Sengupta, Anirban
2014Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesisSengupta, Anirban; Mishra, Vipul Kumar
2017A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODECSengupta, Anirban; Roy, Dipanjan

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