1. IDR@IIT Indore

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Results 1-10 of 22 (Search time: 0.002 seconds).
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Issue DateTitleAuthor(s)
2024Secure FFT IP using C way Partitioning based Obfuscation and FingerprintSengupta, Anirban; Chaurasia, Rahul
2024Secure Accelerated Computing: High-Level Synthesis Based Hardware Accelerator Design for CNN ApplicationsChaurasia, Rahul; Sengupta, Anirban
2024Hardware Security of Image Processing Cores Against IP Piracy Using PSO-Based HLS-Driven Multi-Stage Encryption Fused with Fingerprint SignatureSengupta, Anirban; Anshul, Aditya
2024Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLSChaurasia, Rahul; Sengupta, Anirban
2024Securing Reusable IP Cores Using Voice Biometric Based WatermarkAnshul, Aditya; Sengupta, Anirban
2025High Level Synthesis Based Forensic Watermarking of Hardware IPs using IP Vendor’s DNA SignatureSengupta, Anirban; Bhui, Nabendu; Anshul, Aditya
2024Designing Optimal Secure Hardware IPs for Consumer Electronics using Fingerprint Watermark and Evolutionary Algorithm FrameworkSengupta, Anirban; Chourasia, Vishal; Kumar, Nilesh; Dawar, Praveen
2014Error masking of transient faults: Exploration of a fault tolerant datapath based on user specified power and delay budgetSengupta, Anirban
2024HLS Based Rapid Pareto Front Search of Watermarked Convolutional Layer IP DesignSengupta, Anirban; Chourasia, Vishal;
2024SecureHD: Designing Low-Cost Reliable and Security Aware Hardware Accelerators During High-Level Synthesis for Computationally Intensive Application FrameworksChaurasia, Rahul; Sengupta, Anirban

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