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Issue Date	Title	Author(s)
2017	Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis	Roy, Dipanjan; Sengupta, Anirban
2022	IP Core Protection of Image Processing Filters with Multi-Level Encryption and Covert Steganographic Security Constraints	Anshul, Aditya; Sengupta, Anirban
2015	Design space exploration of datapath (architecture) in high-level synthesis for computation intensive applications	Sengupta, Anirban
2018	Comprehensive operation chaining based schedule delay estimation during high level synthesis	Mishra, Vipul Kumar; Sengupta, Anirban
2017	Low-cost security aware HLS methodology	Sengupta, Anirban
2019	Low cost dual-phase watermark for protecting CE devices in IoT framework	Sengupta, Anirban; Roy, Dipanjan
2016	Embedding low cost optimal watermark during high level synthesis for reusable IP core protection	Sengupta, Anirban
2018	A firefly algorithm driven approach for high level synthesis	Sengupta, Anirban; Rathlavat, Santosh
2014	Time varying vs. fixed acceleration coefficient PSO driven exploration during high level synthesis: Performance and quality assessment	Sengupta, Anirban; Mishra, Vipul Kumar
2016	Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors	Kachave, Deepak; Sengupta, Anirban