IDR@IIT Indore: Search

Search

Search:
for

Current filters:

Start a new search

Add filters:

Results/Page | Sort items by In order Authors/record

Results 1-9 of 9 (Search time: 0.001 seconds).

previous
1
next

Item hits:

Issue Date	Title	Author(s)
2018	Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters]	Kachave, Deepak; Sengupta, Anirban
2016	Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors	Kachave, Deepak; Sengupta, Anirban
2018	Effect of NBTI stress on DSP cores used in CE devices: Threat model and performance estimation	Kachave, Deepak; Sengupta, Anirban; Neema, Shubha; Harsha, Panugothu Sri
2019	Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking	Sengupta, Anirban; Kachave, Deepak; Roy, Dipanjan
2017	Low cost fault tolerance against kc-cycle and km-unit transient for loop based control data flow graphs during physically aware high level synthesis	Sengupta, Anirban; Kachave, Deepak
2018	Spatial and Temporal Redundancy for Transient Fault-Tolerant Datapath	Sengupta, Anirban; Kachave, Deepak
2019	Fault-Tolerant DSP Core Datapath Against Omnidirectional Spatial Impact of SET	Kachave, Deepak; Sengupta, Anirban
2019	Digital Processing Core Performance Degradation Due to Hardware Stress Attacks	Kachave, Deepak; Sengupta, Anirban
2018	Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis	Sengupta, Anirban; Kachave, Deepak