1. IDR@IIT Indore

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Results 1-10 of 97 (Search time: 0.001 seconds).
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Issue DateTitleAuthor(s)
2017Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesisRoy, Dipanjan; Sengupta, Anirban
2015Design space exploration of datapath (architecture) in high-level synthesis for computation intensive applicationsSengupta, Anirban
2013D-logic exploration: Rapid search of Pareto fronts during architectural synthesis of custom processorsSengupta, Anirban; Mishra, Vipul Kumar
2017DSP design protection in CE through algorithmic transformation based structural obfuscationSengupta, Anirban; Roy, Dipanjan
2018Comprehensive operation chaining based schedule delay estimation during high level synthesisMishra, Vipul Kumar; Sengupta, Anirban
2014Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesisSengupta, Anirban; Mishra, Vipul Kumar
2017A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODECSengupta, Anirban; Roy, Dipanjan
2017Low-cost security aware HLS methodologySengupta, Anirban
2017Hardware Vulnerabilities and Their Effects on CE Devices: Design for Security Against Trojans [Hardware Matters]Sengupta, Anirban
2014MO-PSE: Adaptive multi-objective particle swarm optimization based design space exploration in architectural synthesis for application specific processor designMishra, Vipul Kumar; Sengupta, Anirban

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