1. IDR@IIT Indore

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Results 1-10 of 69 (Search time: 0.002 seconds).
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Issue DateTitleAuthor(s)
2022IP Core Protection of Image Processing Filters with Multi-Level Encryption and Covert Steganographic Security ConstraintsAnshul, Aditya; Sengupta, Anirban
2013D-logic exploration: Rapid search of Pareto fronts during architectural synthesis of custom processorsSengupta, Anirban; Mishra, Vipul Kumar
2018Comprehensive operation chaining based schedule delay estimation during high level synthesisMishra, Vipul Kumar; Sengupta, Anirban
2014Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesisSengupta, Anirban; Mishra, Vipul Kumar
2024HLS driven Hybrid GA-PSO for Design Space Exploration of Optimal Palmprint Biometric based IP Watermark and Loop Unrolling FactorSengupta, Anirban; Chourasia, Vishal; Kumar, Nitish Sai
2024SWIFT: Swarm Intelligence Driven ESL Synthesis for Functional Trojan FortificationSengupta, Anirban
2024Secure Accelerated Computing: High-Level Synthesis Based Hardware Accelerator Design for CNN ApplicationsChaurasia, Rahul; Sengupta, Anirban
2023Hardware Security of Digital Image Filter IP Cores against Piracy using IP Seller's Fingerprint Encrypted Amino Acid Biometric SampleSengupta, Anirban; Chaurasia, Rahul; Anshul, Aditya
2023Securing Fault-Detectable CNN Hardware Accelerator Against False Claim of IP Ownership Using Embedded Fingerprint as CountermeasureSengupta, Anirban; Chaurasia, Rahul
2016Embedding low cost optimal watermark during high level synthesis for reusable IP core protectionSengupta, Anirban

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