Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/10128
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dc.contributor.authorRathor, Mahendraen_US
dc.contributor.authorSengupta, Anirbanen_US
dc.date.accessioned2022-05-23T13:56:50Z-
dc.date.available2022-05-23T13:56:50Z-
dc.date.issued2022-
dc.identifier.citationRathor, M., & Sengupta, A. (2022). Particle Swarm Optimization-Driven DSE-Based Low-Cost Hardware Security for Securing DSP IP Cores. In S. K. Shandilya, N. Wagner, V. B. Gupta, & A. K. Nagar (Eds.), Advances in Nature-Inspired Cyber Security and Resilience (pp. 29�54). Springer International Publishing. https://doi.org/10.1007/978-3-030-90708-2_3en_US
dc.identifier.issn2522-8595-
dc.identifier.otherEID(2-s2.0-85129129633)-
dc.identifier.urihttps://doi.org/10.1007/978-3-030-90708-2_3-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/10128-
dc.description.abstractThe digital signal processing (DSP)-based intellectual property (IP) cores are massively being integrated in the modern system-on-chips (SoCs) developed for consumer electronic systems. The reason behind the thriving of DSP-based chips in the consumer electronics market is the vital role of DSP algorithms to perform functions such as filtering (de-noising), data compression-decompression, encoding-decoding etc. However the journey of a DSP-based IP core from its algorithmic form to an IP block within an end SoC is susceptible to hardware threats such as possible hardware Trojan (malicious logic) insertion, IP misuse and fraud claim. This is due to the involvement of more than one design house (fabless and foundry) in the integrated circuit (IC) design chain. For example: (i) Components or IP blocks used in the high-level synthesis (HLS) design process may be Trojan infected as they are supplied by a distinct third-party IP (3PIP) vendor. Thus integrated malicious components in the chip design may cause failure during critical operations. (ii) An IP core design of a genuine vendor may be illegally misused by an adversary in an untrustworthy design house or foundry. These threats of Trojan insertion and IP misuse can be handled during the HLS design process of an IP core. However, employing security techniques may result in design overhead in terms of additional hardware area and latency. This challenge can be addressed by integrating a particle swarm optimization (PSO, a nature-inspired algorithm)-based design space exploration (DSE) process with the HLS design process to explore a low-cost security solution. This chapter discusses (i) a PSO-DSE-driven low-cost Trojan security-aware HLS technique to enable the detection of hidden Trojan in the design components and (ii) a PSO-DSE-driven low-cost watermark security-aware HLS technique to enable the detection of IP piracy and nullification of fraud claim of IP ownership. © 2022, The Author(s), under exclusive license to Springer Nature Switzerland AG.en_US
dc.language.isoenen_US
dc.publisherSpringer Science and Business Media Deutschland GmbHen_US
dc.sourceEAI/Springer Innovations in Communication and Computingen_US
dc.subjectCostsen_US
dc.subjectCrimeen_US
dc.subjectDigital signal processingen_US
dc.subjectFoundriesen_US
dc.subjectHardware securityen_US
dc.subjectIntellectual propertyen_US
dc.subjectIntellectual property coreen_US
dc.subjectMalwareen_US
dc.subjectParticle swarm optimization (PSO)en_US
dc.subjectProgrammable logic controllersen_US
dc.subjectSystem-on-chipen_US
dc.subjectWatermarkingen_US
dc.subjectDesign houseen_US
dc.subjectDesign space explorationen_US
dc.subjectDesign-processen_US
dc.subjectHigh-level synthesisen_US
dc.subjectIntellectual property piracyen_US
dc.subjectLow-costsen_US
dc.subjectSynthesis designen_US
dc.subjectTrojan detectionsen_US
dc.subjectTrojansen_US
dc.subjectWatermarken_US
dc.subjectHigh level synthesisen_US
dc.titleParticle Swarm Optimization-Driven DSE-Based Low-Cost Hardware Security for Securing DSP IP Coresen_US
dc.typeBook Chapteren_US
Appears in Collections:Department of Computer Science and Engineering

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