A 5.5-GHz Low-Power Divide-By-8/9 Dual Modulus Prescaler Using Pulse Extension Logic

Abstract

This paper presents a new optimized high-speed divide-by-8/9 dual modulus prescaler. Simulation results show 54% reduction in power consumption, 40% of speed improvement and almost 48% area reduction as compared to the conventional architecture. Power consumption in the proposed prescaler is reduced by eliminating one True-Single-Phase Clocked (TSPC) D Flip-Flop (DFF) from the standard divide-by-2/3 prescaler, replacing it with Pulse Extension Logic (PEL) circuit. Redundant stages from asynchronous divide-by-2 units were also removed to save more power and reduce more delay. The simulation results show that the prescaler is capable of running at 5.5GHz of maximum frequency with 1.9mW power consumption. The divider is implemented in 0.18-m CMOS technology with 1.8V power supply. © 2022 World Scientific Publishing Company.