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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Raut, Gopal | en_US |
dc.contributor.author | Vishvakarma, Santosh Kumar | en_US |
dc.date.accessioned | 2022-11-21T14:27:23Z | - |
dc.date.available | 2022-11-21T14:27:23Z | - |
dc.date.issued | 2022 | - |
dc.identifier.citation | Rangarajan, N., Patnaik, S., Nabeel, M., Ashraf, M., Rai, S., Raut, G., . . . Sinanoglu, O. (2022). SCRAMBLE: A secure and configurable, memristor-based neuromorphic hardware leveraging 3D architecture. Paper presented at the Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, , 2022-July 308-313. doi:10.1109/ISVLSI54635.2022.00067 Retrieved from www.scopus.com | en_US |
dc.identifier.isbn | 978-1665466059 | - |
dc.identifier.issn | 2159-3469 | - |
dc.identifier.other | EID(2-s2.0-85140920230) | - |
dc.identifier.uri | https://doi.org/10.1109/ISVLSI54635.2022.00067 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/11082 | - |
dc.description.abstract | In this work we present SCRAMBLE, a configurable neuromorphic architecture that provides security against different threats by employing memristors for critical parts and functions. More specifically, we employ memristive memory cells - that are 3D stacked on top of the configurable neuromorphic hardware - to securely hold the weights as well as activation functions of any model processed on the generalized architecture. Thus, programmable memristive cells enable reconfiguration of the architecture to thwart both model stealing and hardware IP stealing attacks. We implement a proof-of-concept for the proposed architecture and analyze its security metrics. We also benchmark it against selected prior art for neuromorphic architectures to quantify the security-performance trade-offs. © 2022 IEEE. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE Computer Society | en_US |
dc.source | Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI | en_US |
dc.subject | Benchmarking | en_US |
dc.subject | Economic and social effects | en_US |
dc.subject | Three dimensional integrated circuits | en_US |
dc.subject | 3D architectures | en_US |
dc.subject | Activation functions | en_US |
dc.subject | Hardware IP | en_US |
dc.subject | Memory cell | en_US |
dc.subject | Memristor | en_US |
dc.subject | Neuromorphic Architectures | en_US |
dc.subject | Neuromorphic hardwares | en_US |
dc.subject | Proof of concept | en_US |
dc.subject | Proposed architectures | en_US |
dc.subject | Weight functions | en_US |
dc.subject | Memristors | en_US |
dc.title | SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture | en_US |
dc.type | Conference Paper | en_US |
Appears in Collections: | Department of Electrical Engineering |
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