Performance assessment of scaled charge trap flash memory cell for improved reliability

Abstract

Semiconductor memory devices have been driving the Silicon (Si) integrated circuit technology for years. The strong increase in the demand for portable electronic gadgets has driven the exceptional growth of non-volatile memory. The advent of advanced technologies, such as the Internet of Things (IoT) and Artificial Intelligence (AI), makes a significant contribution as well. While the digital age has offered several consumer benefits, the stringent requirements on memory in terms of density, cost, power consumption, and speed are the crucial challenges. Moore’s law, along with the scaling theory proposed by Dennard et al., has driven the continuous increase in memory density along with cost improvements. As the gate length scaling is now entering the sub 20 nm node, the scalability of the standard storage cell is approaching its scaling limits due to the requirement of a thicker gate stack. While the previously reported results on NAND flash memory devices are promising, the focus has shifted towards the use of emerging device architectures and non-conventional programming/erasing schemes to further improve the reliability and scalability of the flash memory cell. Thus, the thesis work explores the possible solutions to overcome various scaling challenges associated with the present flash technology. The key contribution of this research is to provide insights into the physical phenomenon occurring in the flash memory cell, which influences the memory operation. The thesis work reports on the device perspective, where the memory operation of the flash memory cell can be improved by appropriate selection of the device architecture.