An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array

Abstract

To conquer the drawback of von Neumann architecture, research has been carried out on the computational methods in the memory array itself to achieve near-memory or in-memory computations (IMC). This paper for the first time proposed an analog IMC approach for full adder design using 8 + T Static Random Access Memories (SRAM). In conventional FA, addition is executed as a sequence of digital boolean operations inside the memory array and there is a need for external logic gates to compute the FA outputs. The proposed analog adder exploits the bit-line voltage discharge (V BL ) with respect to the data stored in the 8 + T memory cell for the bit addition. The bit-line discharge voltage is accumulated using a voltage accumulation circuit (VAC) and acts as an input to an analog to digital converter (ADC). The digital output obtained is the Sum of a single bit FA. Multi-bit FA is computed from this single-bit analog FA. Extensive simulation results, referring to an industrial hardware-calibrated UMC 65-nm CMOS technology indicate 27 × improvement in power and 36 × improvements in throughput leading to a reduction of 972 × in energy-delay product. © 2022, The Author(s), under exclusive license to Springer Nature Switzerland AG.