IP Core Protection of Image Processing Filters with Multi-Level Encryption and Covert Steganographic Security Constraints

Abstract

Image processing-based hardware accelerators are extensively used in consumer electronics devices and applications. Image processing intellectual property (IP) cores such as blur filter, sharpening filter, laplace edge detection filter, etc., are some essential IP cores used in these image processing-based hardware accelerators. Security of these image processing IP cores is crucial as they perform critical real-world functions such as medical imagining, character recognition, etc. This paper presents a novel hardware security technique for IP core protection of image processing filters with multi-level encryption and steganographic security constraints. This paper presents signature-based hardware security methodology on image processing IP cores for the first time. Further, the paper presents embedding hardware security constraints generated with multi-level encryption and steganographic constraints on blur filter application using a high-level synthesis framework. The article also reports the design cost (in terms of delay and area) of the proposed methodology corresponding to different filters and a lower probability of coincidence, indicating the robustness of the proposed approach. © 2022 IEEE.