Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/11639
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dc.contributor.authorChaurasia, Rahulen_US
dc.contributor.authorSengupta, Anirbanen_US
dc.date.accessioned2023-05-03T15:04:29Z-
dc.date.available2023-05-03T15:04:29Z-
dc.date.issued2022-
dc.identifier.citationChaurasia, R., & Sengupta, A. (2022). Crypto-genome signature for securing hardware accelerators. Paper presented at the INDICON 2022 - 2022 IEEE 19th India Council International Conference, doi:10.1109/INDICON56171.2022.10039955 Retrieved from www.scopus.comen_US
dc.identifier.otherEID(2-s2.0-85149259825)-
dc.identifier.urihttps://doi.org/10.1109/INDICON56171.2022.10039955-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/11639-
dc.description.abstractThis paper presents a new crypto-Genome signature-based security methodology to secure hardware accelerators against IP piracy and ownership threats. In the proposed approach, an IP vendor selected Genome sequence is formulated using two different types of base pair/order of Genome chemical elements: Guanine (G), Thymine (T), Adenine (A), Cytosine (C) and polynucleotide (S), followed by robust encryption using unified Feistel cipher process and encodings. This IP vendor's crypto-Genome signature is then subsequently transformed into its corresponding digital template, followed by embedding into the design as covert crypto-genome signature security constraintsen_US
dc.description.abstractthus, enabling the security of hardware accelerator design. The proposed methodology renders robust security than recent hardware steganography and facial biometric based hardware security approaches proposed in the literature on the grounds of definite proof of ownership (authorship) and tamper tolerance ability. The proposed crypto-Genome signature approach offers: (a) lesser value of probability of coincidence (Pc) metric (signifying strength of digital proof) ranging from 7.52E-4 to 9.00E-14en_US
dc.description.abstract(b) robust tamper tolerance ability (TT) of DSP hardware accelerators ranging from 3.3E+7 to 5.39E+67. © 2022 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceINDICON 2022 - 2022 IEEE 19th India Council International Conferenceen_US
dc.subjectChemical elementsen_US
dc.subjectComputer hardwareen_US
dc.subjectCryptographyen_US
dc.subjectDigital signal processingen_US
dc.subjectBase pairsen_US
dc.subjectCounterfeitingen_US
dc.subjectDSPen_US
dc.subjectGenome sequencesen_US
dc.subjectGuanineen_US
dc.subjectHardware acceleratorsen_US
dc.subjectIP vendorsen_US
dc.subjectPolynucleotidesen_US
dc.subjectSecurityen_US
dc.subjectSecurity methodologiesen_US
dc.subjectGenesen_US
dc.titleCrypto-Genome Signature for Securing Hardware Acceleratorsen_US
dc.typeConference Paperen_US
Appears in Collections:Department of Computer Science and Engineering

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