Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/11937
Title: Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key
Authors: Sengupta, Anirban
Chaurasia, Rahul
Anshul, Aditya
Keywords: Hardware accelerator;intellectual property (IP) cores;security
Issue Date: 2023
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Sengupta, A., Chaurasia, R., & Anshul, A. (2023). Robust security of hardware accelerators using protein molecular biometric signature and facial biometric encryption key. IEEE Transactions on very Large Scale Integration (VLSI) Systems, 31(6), 826-839. doi:10.1109/TVLSI.2023.3265559
Abstract: This article proposes a robust encrypted protein molecular biometric signature-based hardware security approach to secure hardware accelerators (like digital signal processing (DSP) and multimedia intellectual property (IP) cores) against threats of piracy/IP counterfeiting and ownership abuse. In the proposed approach, protein molecular biometric signature is formulated by taking the protein sequence of 20 different unique amino acid combinations from human body protein sample, followed by robust encryption using facial biometric key and encodings. This IP vendor's encrypted protein molecular biometric signature is then subsequently converted into its corresponding digital proof, followed by embedding into the design as a covert protein molecular signature security constraint, thus producing a secured hardware accelerator design. The proposed approach is more robust than recent hardware security approaches proposed in the literature in terms of stronger proof of ownership (authorship) as well as tamper tolerance (TT) ability. The results present the following analysis of the proposed protein molecular biometric signature approach: 1) very low probability of coincidence (Pc) metric (signifying strength of digital proof) for different DSP hardware accelerators in the range of 3.40E-13-6.33E-2 and 2) stronger TT ability in the range of 5.39E + 67-1.0E + 421 for different DSP hardware accelerators. © 1993-2012 IEEE.
URI: https://doi.org/10.1109/TVLSI.2023.3265559
https://dspace.iiti.ac.in/handle/123456789/11937
ISSN: 1063-8210
Type of Material: Journal Article
Appears in Collections:Department of Computer Science and Engineering

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