Hardware (IP) Watermarking During Behavioral Synthesis

Abstract

The current generation of Consumer Electronics (CE) systems includes Digital Signal Processing (DSP) hardware as an essential constituent. Without these imperative data-intensive high-performance cores, much of the vital consumer applications including image/video/audio processing functions would not be possible in the modern electronic devices. Owing to the importance of such Intellectual Property (IP) cores, its security against standard threats cannot be undermined. Securing a DSP core against false claim of ownership and piracy is very crucial due to globalization aspect leading to multinational, distributed, and multi-step nature of Integrated Circuit (IC) design process, which in turn contributes toward vulnerability related to hardware trust. This chapter discusses the state-of-the-art approaches on hardware watermarking during behavioral synthesis as a solution to the aforesaid problem. This chapter presents various high-level synthesis-based techniques with emphasis on single-phase, triple-phase watermarking techniques, digital signature-based watermarking, binary encoding-based watermarking, and in-synthesis-based watermarking used for reusable IP cores (for DSP/multimedia applications). Demonstrative examples have been provided for illustrations of these approaches. The chapter also discusses algorithm used for generating low-cost optimal watermark during behavioral synthesis as well as the important threat scenarios and desirable properties necessary for IP watermarking. The chapter finally concludes with discussions on several case studies (DSP cores) in the context of some important watermarking techniques. © Springer Nature Switzerland AG 2022.