Analysis of ferroelectric gate stack induced steep switching and negative differential resistance in MOSFET for ultra low power applications

Abstract

Logic functionality of Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) primarily depends on the subthreshold swing (SSwing = FB×FT, where FB is the body factor and FT is transport factor) which is in turn governed by gate bias (VGS) required to change the drain current (IDS) by one decade. In conventional MOSFETs, SSwing is limited to 60 mV/dec due to its current conduction mechanism (FT ≈ 60 mV/dec) and gate-to-channel coupling (FB = 1+(CCH/CINS) ≥ 1, where CCH is channel capacitance and CINS is gate insulator capacitance). Consequently, this limit leads to elevated static power dissipation in downscaled devices. Hence, transistors with SSwing lower than 60 mV/decade are highly desirable. Negative capacitance (NC) FETs can overcome Boltzmann switching limit (60 mV/dec) due to their ability to lower FB below 1 by utilizing the NC phenomena of ferroelectric at gate stack. NCFETs can be implemented through two topologies (i) Metal-Ferroelectric-Insulator-Semiconductor (MFIS), where the ferroelectric layer is deposited over the gate oxide, and (ii) Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) where the metal layer is inserted between the ferroelectric layer and gate oxide insulator layer. In this thesis, both topologies are considered with multigate transistors such as double gate (DG) and gate-all-around (GAA) cylindrical (CYL) geometry due to their better gate controllability.