In-Memory Computing with 6T SRAM for Multi-operator Logic Design

Abstract

This article presents a reconfigurable in-/near-memory advanced computing (InMAC) architecture based on 6T SRAM, with a storage capacity of 1 KB (128 × 64). The proposed architecture utilizes standard 65 nm CMOS technology and operates with a power supply of 1 V. Along with standard storage operations, the design performs various complex Boolean computing operations, such as binary to gray, gray to binary, 2’s complement, and binary addition, with 8-bit precision. The architecture also implements other essential logic operations, such as NAND, NOR, XOR, and XNOR, in an area-efficient manner, without requiring complex circuitry. The design offers flexibility in the reconfiguration to meet specific bit precision and operation requirements. In-memory computing approaches improve the latency by 7 × and 4 × for logic implementation and Boolean computation, respectively, compared to conversions performed outside the macro. Additionally, the optimized full adder design outperforms the state-of-the-art design in terms of all parameters analyzed, with reductions of 40% in the number of transistors, 25.4% in latency, 55.2% in dynamic power, and 28.1% in static power. The proposed InMAC architecture can potentially use in-memory computing in various applications that require advanced computing with low latency. © 2023, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.