SRAM Process and Debug Sensor

Abstract

In this paper, a RAZOR-based in-situ monitoring scheme is described for process variation characterization and silicon debug in SRAM arrays. The scheme can identify whether the datapath being monitored has slowed-down due to process variation or hard errors. This information can be used to estimate the impact of process variation or hard errors on memory access time setting critical path in SRAM arrays. Pre-silicon characterized datapath delay via selectable data delay lines referred to as data TRIMs are obtained via SPICE simulations. These pre-silicon data TRIMs, along with post-silicon error output can be used to estimate the datapath slow-down with a margin of error. The margin of error can be reduced by using finer granularity in data TRIMs but comes at the cost of area and power overheads. The scheme can be shared across multiple SRAM arrays, and can also be used in a column-by-column manner to test memory access time with respect to individual bitcells in an array. This provides a deep level of visibility into SRAM macros post-silicon for debug purposes too. The scheme can estimate the slow-down on memory access time setting critical path in global TT corner with up to 99.2 % accuracy. © 2023 IEEE.