Secured and Optimized Hardware Accelerators using Key-Controlled Encoded Hash Slices and Firefly Algorithm based Exploration

Abstract

The design process of application-specific integrated circuits (ASICs) as hardware accelerators or reusable hardware intellectual property (IP) cores require considering various design goals like area, latency, and security against attacks such as IP piracy and false claims of IP ownership during architectural synthesis. The problem of IP piracy and false IP ownership claim poses a significant threat to hardware IP cores, jeopardizing innovation, fair competition, and economic growth. The proposed work introduces a novel security framework to design secured and optimized hardware accelerators using key-controlled encoded hash slices integrated with firefly algorithm (FF) based design space exploration (DSE) during high level synthesis (HLS). The proposed methodology also demonstrates the embedding of covert security constraints into an optimal 8-point DCT hardware IP design, obtained by performing a tradeoff between area and latency through the FF-based DSE. The proposed methodology achieves stronger tamper tolerance and entropy than recent approaches. The experimental results also provide design cost assessment and optimality analysis. © 2023 IEEE.