SRAM Vmin Scaling via Negative Wordline

Abstract

The noise margin during the write operation in SRAMs is investigated by implementing a negative bitline voltage scheme in this paper. Negative bitline improves the write static noise margin of the SRAM bitcells during a write operation

however, this can cause degraded hold static noise margin of unaccessed cells in the array, called column half-select. Applying a negative wordline voltage on unaccessed rows in an array under negative bitline shows that the degraded hold static noise margin of unaccessed cells can be improved. Fundamentally, the dependence of negative bitline on Vmin,hold of unaccessed cells is negated by applying negative wordline. This allows for a more aggressive scaling of Vmin,hold, resulting in a 77.8% reduction in static power. By applying a complementary negative wordline voltage to counter the half-select condition in columns, the write static noise margin of cells in accessed rows was also boosted by 23% without any degradation in hold static margins of unaccessed cells. © 2023 IEEE.