Low-Cost Hardware Security of Laplace Edge Detection and Embossment Filter Using HLS Based Encryption and PSO

Abstract

The broad applicability of laplace edge detection and embossment filters in modern electronics and embedded systems has created the urge to design these filters as dedicated reusable intellectual property (IP) cores. Further, it is imperative to consider design optimization along with the security of these filters to generate an optimal secured design flow that has the capability to provide protection against hardware security threats such as IP piracy and fraudulent claim of IP ownership. The proposed approach presents an integrated design flow methodology using particle swarm optimization-driven design space exploration and a high level synthesis (HLS)-based encryption security methodology to generate a secured low-cost laplace edge detection and embossment filter IP cores. The proposed approach facilitates embedding of more significant number of secret hardware security constraints (having a lower probability of coincidence and higher tamper tolerance) at zero design cost overhead. The proposed approach depicts more robust security than prior similar approaches. © 2023 IEEE.