Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/14236
Title: M-HLS: Malevolent High-Level Synthesis for Watermarked Hardware IPs
Authors: Sengupta, Anirban
Anshul, Aditya
Chourasia, Vishal
Kumar, Nitish
Keywords: Degradation;Hardware;HLS;IP networks;Registers;Security;security;Trojan horses;Trojans;watermarked IP;Watermarking
Issue Date: 2024
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Sengupta, A., Anshul, A., Chourasia, V., & Kumar, N. (2024). M-HLS: Malevolent High-Level Synthesis for Watermarked Hardware IPs. IEEE Embedded Systems Letters. https://doi.org/10.1109/LES.2024.3416422
Abstract: Hardware Trojan insertion in high-level synthesis (HLS) generated intellectual property (IP) designs can pose strong security concern for the designers. Backdoor hardware Trojans can be inserted in the HLS design flow to compromise the produced register transfer level (RTL) IP design. This paper presents a novel malevolent HLS (M-HLS) framework introducing the possibility of two different hardware Trojan insertion (i.e., performance degradation hardware Trojan (PDHT) and denial-of-service hardware Trojan (DoS-HT)) in multiplexer (mux)-based interconnect stage of HLS generated watermarked IP design. The proposed framework is validated on watermarked MESA Horner Bezier&#x2019
s IP, which indicates strong performance degradation and denial of service achievable by an attacker at minimal area and power overhead. IEEE
URI: https://doi.org/10.1109/LES.2024.3416422
https://dspace.iiti.ac.in/handle/123456789/14236
ISSN: 1943-0663
Type of Material: Journal Article
Appears in Collections:Department of Computer Science and Engineering

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