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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/14237
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dc.contributor.authorSemwal, Sandeepen_US
dc.contributor.authorNirala, Rohit Kumaren_US
dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2024-08-14T10:23:45Z-
dc.date.available2024-08-14T10:23:45Z-
dc.date.issued2024-
dc.identifier.citationSemwal, S., Nirala, R. K., Gupta, M., & Kranti, A. (2024). Extremely High Noise Margin and Low Leakage in ULP Circuits with NCFETs. 2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings. https://doi.org/10.1109/VLSITSA60681.2024.10546420en_US
dc.identifier.isbn979-8350360349-
dc.identifier.otherEID(2-s2.0-85196738243)-
dc.identifier.urihttps://doi.org/10.1109/VLSITSA60681.2024.10546420-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/14237-
dc.description.abstractThe efficacy of negative capacitance transistors (NC-T) to implement ultralow power (ULP) subthreshold logic blocks such as inverter, diode, composite transistor (CT) based diode, n-type and p-type CT, and CT inverter is reported through simulations and analytical model. ULP logic blocks with NC-T are shown to exhibit (i) improved noise margin ( 80% of supply voltage (VDD)), (ii) wider hysteresis window ( 0.9 VDD), (iii) suppressed reverse saturation current (10-14 A) in CT diode, and (iv) signif-icantly lower off-current (∼8 ×10-15 A) in n-type CT. © 2024 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.source2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedingsen_US
dc.titleExtremely High Noise Margin and Low Leakage in ULP Circuits with NCFETsen_US
dc.typeConference Paperen_US
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