Memristor-based digital logic circuit design

Abstract

The limitations of existing complementary metal-oxide-semiconductor (CMOS) technology in terms of area and power efficiency have catalyzed advanced research into alternative nanodevices. Memristors, with their unique switching properties, offes a promising avenue for replacing traditional CMOS technology in edge computing devices. This thesis presents the design, implementation, and performance evaluation of memristor-based combinational logic circuits, including adders, subtractors, and decoders, utilizing MATLAB Simulink and Cadence Virtuoso. We proposed an optimized design for memristor-based combinational logic circuits and conducted a comparative study with conventional CMOS methods. The memristor model, experimentally validated for a high-density Y2O3-based memristive crossbar array which demonstrates ultralow device-to-device and cycle-to-cycle variability. Our findings indicate a power reduction of over 90% compared to CMOS technology implemented in Cadence Virtuoso, alongside a significant reduction in the number of components, enhancing area efficiency and facilitating the design of complex logic circuits on a micrometer scale.