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https://dspace.iiti.ac.in/handle/123456789/14975
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Sengupta, Anirban | en_US |
| dc.contributor.author | Chourasia, Vishal | en_US |
| dc.contributor.author | Anshul, Aditya | en_US |
| dc.date.accessioned | 2024-12-18T10:34:11Z | - |
| dc.date.available | 2024-12-18T10:34:11Z | - |
| dc.date.issued | 2024 | - |
| dc.identifier.citation | Sengupta, A., Chourasia, V., & Anshul, A. (2024). HLS Scheduling Driven Encoded Watermarking for Secure Convolutional Layer IP Design in CNN. 11th IEEE International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2024. Scopus. https://doi.org/10.1109/ICCE-Taiwan62264.2024.10674266 | en_US |
| dc.identifier.isbn | 979-8350386844 | - |
| dc.identifier.other | EID(2-s2.0-85205807396) | - |
| dc.identifier.uri | https://doi.org/10.1109/ICCE-Taiwan62264.2024.10674266 | - |
| dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/14975 | - |
| dc.description.abstract | This paper presents a novel high level synthesis (HLS) scheduling driven robust watermarking methodology for convolutional layer intellectual property (IP) design in convolutional neural network (CNN), useful for consumer electronics (CE) systems. The results of proposed approach yielded enhanced security in terms of tamper tolerance stronger entropy than prior works, at nominal design/latency overhead. © 2024 IEEE. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
| dc.source | 11th IEEE International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2024 | en_US |
| dc.title | HLS Scheduling Driven Encoded Watermarking for Secure Convolutional Layer IP Design in CNN | en_US |
| dc.type | Conference Paper | en_US |
| Appears in Collections: | Department of Computer Science and Engineering | |
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