HOAA: Hybrid Overestimating Approximate Adder for Enhanced Performance Processing Engine

Abstract

This paper presents the Hybrid Overestimating Approximate Adder designed to enhance the performance in processing engines, specifically focused on edge-AI applications. A novel Plus One Adder design is proposed as an incremental adder in the RCA chain, incorporating a Full Adder with an excess-1 alongside inputs A, B, and Cin. The design approximates outputs to 2-bit values to reduce hardware complexity and improve resource efficiency. The Plus One Adder is integrated into a dynamically reconfigurable HOAA, allowing runtime interchangeability between accurate and approximate overestimation modes. The proposed design is demonstrated for multiple applications, such as Two's complement subtraction and Rounding-to-even, and the Configurable Activation function, which are critical components of the Processing engine. Our approach shows a 21% improvement in area efficiency and a 33% reduction in power consumption, compared to state-of-the-art designs with minimal accuracy loss. Thus, the proposed HOAA could be a promising solution for resource-constrained environments, offering ideal trade-offs between hardware efficiency vs computational accuracy. © 2024 IEEE.