Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/15191
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dc.contributor.authorSengupta, Anirbanen_US
dc.contributor.authorAnshul, Adityaen_US
dc.date.accessioned2024-12-24T05:20:10Z-
dc.date.available2024-12-24T05:20:10Z-
dc.date.issued2024-
dc.identifier.citationSengupta, A., & Anshul, A. (2024). High-level synthesis-based watermarking using multimodal biometric. In A. Sengupta, High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection (pp. 109–135). Institution of Engineering and Technology. https://doi.org/10.1049/PBCS084E_ch5en_US
dc.identifier.otherEID(2-s2.0-85211842589)-
dc.identifier.urihttps://doi.org/10.1049/PBCS084E_ch5-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/15191-
dc.description.abstractThis chapter discusses hardware security methodologies for securing the transient fault-secured hardware intellectual property (IP) designs using unified multimodal biometric and an encoded dictionary. The explained framework leverages a high-level synthesis (HLS) process to create transient fault-secured hardware IPs. Further, it integrates encoded unified biometric-based hardware security constraints into the hardware design to protect the designs from IP piracy and false IP ownership claim. This ensures the creation of watermarked fault-secured hardware designs, thereby enhancing IP seller’s and end consumer’s safety by mitigating the risk of using pirated/unreliable designs. The discussed watermarking methodologies provide stronger digital evidence for piracy detection and greater resilience against tampering attack. © The Institution of Engineering and Technology and its licensors 2024.en_US
dc.language.isoenen_US
dc.publisherInstitution of Engineering and Technologyen_US
dc.sourceHigh-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protectionen_US
dc.titleHigh-level synthesis-based watermarking using multimodal biometricen_US
dc.typeBook Chapteren_US
Appears in Collections:Department of Computer Science and Engineering

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