Introduction to hardware security and trust and high-level synthesis

Abstract

The chapter provides the readers with a formal introduction to achieving hardware security and trust through high-level synthesis (HLS) followed by its motivation and comprehensive exploration of different hardware attack scenarios and countermeasures. An adversary (situated in different design phases) may potentially leverage various attack scenarios to compromise the confidentiality, integrity, and reliability of electronic systems comprising reusable hardware designs. Addressing these threats necessitates a comprehensive understanding of hardware security and a proactive approach to fortify systems against potential threats. This chapter aims to contribute to the development of secure and trustworthy computing systems by providing a basic foundation for security aware HLS-based hardware design methodology, different attack scenarios, and effective countermeasures. This chapter therefore bridges the gap between the existing hardware security challenges and its advanced countermeasure strategies. The rest of the chapter is structured as follows: Section 1.1 provides the introduction of the chapter including motivation for hardware security and trust

Section 1.2 discusses different attack scenarios

Section 1.3 provides different security countermeasures

Section 1.4 discusses the utility of the HLS framework for integrating security countermeasures

Section 1.5 presents a brief summary of the book

Section 1.6 concludes the chapter by summarizing its significance and implications. © The Institution of Engineering and Technology and its licensors 2024.