Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/15196
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dc.contributor.authorSengupta, Anirbanen_US
dc.contributor.authorChaurasia, Rahulen_US
dc.date.accessioned2024-12-24T05:20:10Z-
dc.date.available2024-12-24T05:20:10Z-
dc.date.issued2024-
dc.identifier.citationSengupta, A., & Chaurasia, R. (2024). Hardware obfuscation-high level synthesis-based structural obfuscation for hardware security and trust. In A. Sengupta, High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection (pp. 187–227). Institution of Engineering and Technology. https://doi.org/10.1049/PBCS084E_ch8en_US
dc.identifier.isbn978-183724118-7-
dc.identifier.isbn978-183724117-0-
dc.identifier.otherEID(2-s2.0-85211876804)-
dc.identifier.urihttps://doi.org/10.1049/PBCS084E_ch8-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/15196-
dc.description.abstractThe chapter describes a high-level synthesis (HLS)-driven methodology for generating secure hardware intellectual property (IP) core design with fault detectability feature using multi-cut-based structural obfuscation and physical biometric (Chaurasia and Sengupta, 2023a). In this methodology, firstly, the IP design is leveraged with transient fault detectability feature and is transformed/obscured using multi-cut-based structural obfuscation. This transformation serves as the first layer of security, ensuring the protection of the design against potential reverse engineering attempts by an adversary. Subsequently, the design is covertly embedded with physical biometric of IP vendor. The embedded naturally unique biometric information of genuine IP vendor serves as the second layer of security, ensuring the protection of the design against IP piracy. Thus, HLS-driven hardware security methodology can concurrently offer security of “fault-detectable IP designs” against the following hardware threats: (a) potential reverse engineering threat by an adversary from the SoC layout stage in an untrustworthy foundry and (b) IP piracy by an adversary that may present in the SoC integration house. The rest of the chapter is structured as follows: Section 8.1 provides the introduction of the chapteren_US
dc.description.abstractSection 8.2 delves into the various threat model scenarioen_US
dc.description.abstractSection 8.3 provides background on transient faulten_US
dc.description.abstractSection 8.4 explores the multi-cut-based structural obfuscation technique and physical biometrics for enhanced hardware IP securityen_US
dc.description.abstractSection 8.5 presents a case study on IIR filter application frameworken_US
dc.description.abstractSection 8.6 presents security features of the methodologyen_US
dc.description.abstractSection 8.7 analyzes the security of IP design achieved through multi-cut based structural obfuscation and physical biometricsen_US
dc.description.abstractSection 8.8 concludes the chapter by summarizing its findings and implications. © The Institution of Engineering and Technology and its licensors 2024.en_US
dc.language.isoenen_US
dc.publisherInstitution of Engineering and Technologyen_US
dc.sourceHigh-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protectionen_US
dc.titleHardware obfuscation-high level synthesis-based structural obfuscation for hardware security and trusten_US
dc.typeBook Chapteren_US
Appears in Collections:Department of Computer Science and Engineering

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