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DC Field | Value | Language |
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dc.contributor.author | Sengupta, Anirban | en_US |
dc.contributor.author | Chaurasia, Rahul | en_US |
dc.date.accessioned | 2024-12-24T05:20:10Z | - |
dc.date.available | 2024-12-24T05:20:10Z | - |
dc.date.issued | 2024 | - |
dc.identifier.citation | Sengupta, A., & Chaurasia, R. (2024). Hardware obfuscation-high level synthesis-based structural obfuscation for hardware security and trust. In A. Sengupta, High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection (pp. 187–227). Institution of Engineering and Technology. https://doi.org/10.1049/PBCS084E_ch8 | en_US |
dc.identifier.isbn | 978-183724118-7 | - |
dc.identifier.isbn | 978-183724117-0 | - |
dc.identifier.other | EID(2-s2.0-85211876804) | - |
dc.identifier.uri | https://doi.org/10.1049/PBCS084E_ch8 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/15196 | - |
dc.description.abstract | The chapter describes a high-level synthesis (HLS)-driven methodology for generating secure hardware intellectual property (IP) core design with fault detectability feature using multi-cut-based structural obfuscation and physical biometric (Chaurasia and Sengupta, 2023a). In this methodology, firstly, the IP design is leveraged with transient fault detectability feature and is transformed/obscured using multi-cut-based structural obfuscation. This transformation serves as the first layer of security, ensuring the protection of the design against potential reverse engineering attempts by an adversary. Subsequently, the design is covertly embedded with physical biometric of IP vendor. The embedded naturally unique biometric information of genuine IP vendor serves as the second layer of security, ensuring the protection of the design against IP piracy. Thus, HLS-driven hardware security methodology can concurrently offer security of “fault-detectable IP designs” against the following hardware threats: (a) potential reverse engineering threat by an adversary from the SoC layout stage in an untrustworthy foundry and (b) IP piracy by an adversary that may present in the SoC integration house. The rest of the chapter is structured as follows: Section 8.1 provides the introduction of the chapter | en_US |
dc.description.abstract | Section 8.2 delves into the various threat model scenario | en_US |
dc.description.abstract | Section 8.3 provides background on transient fault | en_US |
dc.description.abstract | Section 8.4 explores the multi-cut-based structural obfuscation technique and physical biometrics for enhanced hardware IP security | en_US |
dc.description.abstract | Section 8.5 presents a case study on IIR filter application framework | en_US |
dc.description.abstract | Section 8.6 presents security features of the methodology | en_US |
dc.description.abstract | Section 8.7 analyzes the security of IP design achieved through multi-cut based structural obfuscation and physical biometrics | en_US |
dc.description.abstract | Section 8.8 concludes the chapter by summarizing its findings and implications. © The Institution of Engineering and Technology and its licensors 2024. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institution of Engineering and Technology | en_US |
dc.source | High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection | en_US |
dc.title | Hardware obfuscation-high level synthesis-based structural obfuscation for hardware security and trust | en_US |
dc.type | Book Chapter | en_US |
Appears in Collections: | Department of Computer Science and Engineering |
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