Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/15197
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dc.contributor.authorSengupta, Anirbanen_US
dc.contributor.authorChaurasia, Rahulen_US
dc.date.accessioned2024-12-24T05:20:10Z-
dc.date.available2024-12-24T05:20:10Z-
dc.date.issued2024-
dc.identifier.citationSengupta, A., & Chaurasia, R. (2024). Hardware obfuscation-algorithmic transformation-based obfuscation for secure floorplan-driven high-level synthesis. In A. Sengupta, High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection (pp. 229–262). Institution of Engineering and Technology. https://doi.org/10.1049/PBCS084E_ch9en_US
dc.identifier.isbn978-183724118-7-
dc.identifier.isbn978-183724117-0-
dc.identifier.otherEID(2-s2.0-85211880501)-
dc.identifier.urihttps://doi.org/10.1049/PBCS084E_ch9-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/15197-
dc.description.abstractThe chapter describes an integrated methodology that leverages algorithmic transformation-based obfuscation with crypto-watermarking for generating HLS-driven secure floorplan for loop-based IP designs (Sengupta and Kachave, 2017en_US
dc.description.abstractSengupta and Rathor, 2020en_US
dc.description.abstractSengupta et al., 2017). The significance is that most of the modern electronics systems are integrated with complex loop-based applications to perform important functions such as filtering, convolution, image processing, etc. Loop-based applications can deliver efficient performance if designed using dedicated hardware intellectual property (IP) cores using high-level synthesis (HLS). However, globalization in the design supply chain introduces security vulnerabilities during IP design that need robust countermeasures. More explicitly, the chapter presents a discussion on the following: (a) methodology for generating HLS-driven secure floorplan for loop unrolled hardware IPsen_US
dc.description.abstract(b) integration of algorithmic transformation-based obfuscation with crypto-watermarking during HLS to provide sturdy detective countermeasure against IP piracy and false IP ownership claim, while simultaneously reducing latencyen_US
dc.description.abstract(c) security-aware physical design-based HLS that is capable to convert a loop-based high-level code (representing a computation-intensive application) into its respective early secure floorplan that considers watermark embedding information of the datapath modules. The rest of the chapter has been organized as follows: Section 9.1 provides the introduction of the chapteren_US
dc.description.abstractSection 9.2 discusses prior similar methodologiesen_US
dc.description.abstractSection 9.3 provides details on methodology for algorithmic transformation-based obfuscation for secure floorplan-driven HLSen_US
dc.description.abstractSection 9.4 provides a detailed analysis and discussionen_US
dc.description.abstractand Section 9.5 concludes the chapter by summarizing the chapter’s findings and implications. © The Institution of Engineering and Technology and its licensors 2024.en_US
dc.language.isoenen_US
dc.publisherInstitution of Engineering and Technologyen_US
dc.sourceHigh-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protectionen_US
dc.titleHardware obfuscation-algorithmic transformation-based obfuscation for secure floorplan-driven high-level synthesisen_US
dc.typeBook Chapteren_US
Appears in Collections:Department of Computer Science and Engineering

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