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DC Field | Value | Language |
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dc.contributor.author | Sengupta, Anirban | en_US |
dc.contributor.author | Chaurasia, Rahul | en_US |
dc.date.accessioned | 2024-12-24T05:20:10Z | - |
dc.date.available | 2024-12-24T05:20:10Z | - |
dc.date.issued | 2024 | - |
dc.identifier.citation | Sengupta, A., & Chaurasia, R. (2024). Hardware obfuscation-algorithmic transformation-based obfuscation for secure floorplan-driven high-level synthesis. In A. Sengupta, High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection (pp. 229–262). Institution of Engineering and Technology. https://doi.org/10.1049/PBCS084E_ch9 | en_US |
dc.identifier.isbn | 978-183724118-7 | - |
dc.identifier.isbn | 978-183724117-0 | - |
dc.identifier.other | EID(2-s2.0-85211880501) | - |
dc.identifier.uri | https://doi.org/10.1049/PBCS084E_ch9 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/15197 | - |
dc.description.abstract | The chapter describes an integrated methodology that leverages algorithmic transformation-based obfuscation with crypto-watermarking for generating HLS-driven secure floorplan for loop-based IP designs (Sengupta and Kachave, 2017 | en_US |
dc.description.abstract | Sengupta and Rathor, 2020 | en_US |
dc.description.abstract | Sengupta et al., 2017). The significance is that most of the modern electronics systems are integrated with complex loop-based applications to perform important functions such as filtering, convolution, image processing, etc. Loop-based applications can deliver efficient performance if designed using dedicated hardware intellectual property (IP) cores using high-level synthesis (HLS). However, globalization in the design supply chain introduces security vulnerabilities during IP design that need robust countermeasures. More explicitly, the chapter presents a discussion on the following: (a) methodology for generating HLS-driven secure floorplan for loop unrolled hardware IPs | en_US |
dc.description.abstract | (b) integration of algorithmic transformation-based obfuscation with crypto-watermarking during HLS to provide sturdy detective countermeasure against IP piracy and false IP ownership claim, while simultaneously reducing latency | en_US |
dc.description.abstract | (c) security-aware physical design-based HLS that is capable to convert a loop-based high-level code (representing a computation-intensive application) into its respective early secure floorplan that considers watermark embedding information of the datapath modules. The rest of the chapter has been organized as follows: Section 9.1 provides the introduction of the chapter | en_US |
dc.description.abstract | Section 9.2 discusses prior similar methodologies | en_US |
dc.description.abstract | Section 9.3 provides details on methodology for algorithmic transformation-based obfuscation for secure floorplan-driven HLS | en_US |
dc.description.abstract | Section 9.4 provides a detailed analysis and discussion | en_US |
dc.description.abstract | and Section 9.5 concludes the chapter by summarizing the chapter’s findings and implications. © The Institution of Engineering and Technology and its licensors 2024. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institution of Engineering and Technology | en_US |
dc.source | High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection | en_US |
dc.title | Hardware obfuscation-algorithmic transformation-based obfuscation for secure floorplan-driven high-level synthesis | en_US |
dc.type | Book Chapter | en_US |
Appears in Collections: | Department of Computer Science and Engineering |
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