A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency¤

Abstract

Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance (gm) is the main dominant source of frequency and gain (KVCO) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates 3 times variation in KVCO across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5 GHz is developed in 65 nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum KVCO variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4 mW power from 1 V power supply. © World Scientific Publishing Company.