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https://dspace.iiti.ac.in/handle/123456789/15966
Title: | HLS Based Rapid Pareto Front Search of Watermarked Convolutional Layer IP Design |
Authors: | Sengupta, Anirban Chourasia, Vishal |
Keywords: | convolution layer;design space exploration;HLS;IP designs;Pareto front;Watermarking |
Issue Date: | 2024 |
Publisher: | Institute of Electrical and Electronics Engineers Inc. |
Citation: | Sengupta, A., & Chourasia, V. (2024). HLS Based Rapid Pareto Front Search of Watermarked Convolutional Layer IP Design. Proceedings - 10th IEEE International Symposium on Smart Electronic Systems, ISES 2024. https://doi.org/10.1109/iSES63344.2024.00061 |
Abstract: | This paper presents a novel methodology for high level synthesis (HLS) based Pareto front search of watermarked convolutional layer intellectual property (IP) designs. The presented exploration framework is rapidly capable of pruning the design space of watermarked IP designs using a combination of architecture tree configuration and dominance factor logic. Experimental results validate that the proposed approach is capable of providing significant speedup in the exploration time compared to exhaustive analysis. Further, results of security analysis in terms of watermark robustness achieved by the proposed approach against standard attacks of false ownership claim, tampering and watermark collision have also been reported. © 2024 IEEE. |
URI: | https://doi.org/10.1109/iSES63344.2024.00061 https://dspace.iiti.ac.in/handle/123456789/15966 |
Type of Material: | Conference Paper |
Appears in Collections: | Department of Computer Science and Engineering |
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