HLS Watermarking of IP Designs Using Scheduling Driven Key-Based Parallel Switching Framework Integrated With Multimodal Crypto Logic

Abstract

Due to the globalization in the supply chain in the design of integrated circuits, hardware security threats of fraud intellectual property (IP) ownership attack and IP piracy are on the rise. This paper presents a new high level synthesis (HLS) watermarking technique for hardware security of IP designs. The presented HLS watermarking leverages scheduling driven key-based parallel switching framework integrated with multimodal crypto logic such as advanced encryption standard (AES) S-box, Trifid cipher, secure hashing algorithm (SHA)-512. The proposed hardware IP watermarking approach is capable of yielding substantially enhanced tamper tolerance, greater attackers effort in decoding/establishing the original watermark as well as reduced probability of coincidence, compared to prior approaches, at zero design cost overhead. © 2025 Elsevier B.V., All rights reserved.