Design techniques for bias temperature instability aware and soft-error resilient nanoscale circuits

Abstract

Advances in technology scaling have enhances the performance, functionality, transistor density, and reduces power consumption and cost, while the supply voltage is not proportionally scaled. Due to the increasing power density and electric eld in the gate dielectric, the time-dependent variability of the nanoscale integrated circuits (ICs) becomes the major reliability concern. As a result, maintaining the IC reliability at the desired level becomes a sti challenge at both runtime and design time. The signi cant aging e ects are caused by various physical phenomena such as Hot Carrier Injection (HCI), Bias Temperature Instability (BTI), and Time-dependent Dielectric Breakdown (TDDB). However, Negative BTI (NBTI) in the PMOS transistor becomes the dominating component for IC's unreliability. Additionally, at deep submicron technologies, soft-errors due to high energy particles such as neutron and protons, and cosmic rays may cause spurious logic ips that in uence the correctness of the IC. Impact of both NBTI and soft-errors originate from physical/device level; they are spatially and temporally a ects the circuit and system levels. The rise in susceptibility to both soft-errors and aging e ects makes the circuits one of the important concern when it comes to reliability. Addressing the reliability issues with the recent technology nodes, this dissertation investigates the reliability-aware design and management techniques to ensure the reliability and quality of the IC. With our special interest on time-dependent NBTI degradations, we focus our discussion on (i) runtime aging sensor, (ii) mitigation techniques to improve the reliability, (iii) design time NBTI resilient circuits, and (iv) soft-error hardening analysis of the circuits. In order to achieve quantitative management, two on-chip NBTI sensors are proposed to extract the dynamic degradation information from the circuit. Next, we introduce two compensation techniques to manage the stability and performance of 6T SRAM cell under NBTI variation. Further, we proposed a design-time NBTI resilient Schmitt trigger circuit which can be utilized to design NBTI tolerant circuits like SRAM cells. For the rightfulness, we also implemented the ISCAS'89 benchmark circuit using proposed Schmitt trigger circuit. Finally, we conclude the dissertation with soft-error hardening enhancement analysis of NBTI resilient Schmitt trigger and SRAM cell.