Gated logic controlled 10T-SRAM for low-power bidirectional ring oscillators

Abstract

In this paper, we explore an SRAM-based ring oscillator design based on gate logic. The gating logic not only ensures stable operation but also provides flexibility in managing the activation and deactivation of the oscillator, thus reducing power consumption during idle periods. The proposed Gated Logic-based SRAM cell consumes 1.17× and 1.02× lower read and write power respectively than conventional 6T SRAM. A detailed analysis validates this proposed SRAM cell can be a good candidate for implementing the memory-based RO with less number of memory cell utilization. The frequency in the schematic is 1.24× that of the post-layout and frequency variation with temperature and aging to ensure the reliability of the proposed ring oscillator. Further proposed GL-SRAM-RO consumes less power and area utilization than the previous design. The simulation results show bidirectional behavior, making it a suitable candidate for security and power efficiency requirements and integration into resource-constrained environments and embedded systems. © © 2025. Published by Elsevier B.V.