SRAM-based digital processing-in-memory architectures for resource-efficient edge AI acceleration

Abstract

The rapid expansion of AI applications has intensified the focus on energy-efficient and high-throughput compute-in-memory (CIM) operations for resource-constrained Edge-AI platforms. Recently, SRAM-embedded CIM hardware has emerged as a promising solution to mitigate von Neumann bottlenecks and has shown noteworthy improvements in energy efficiency and throughput for matrix-vector multiplication, a significant portion of neural networks. While PVT variations significantly impact traditional analog/mixed-signal (AMS) macros, the DCIM macros are more robust. 2D Interleaved Adder Tree-based DCIM macro that incorporates an 8-transistor SRAM bitcell capable of performing 1-bit multiplications and addressing the bit-flip issue from simultaneous activation of multiple array rows. A 2D interleaved adder tree using a novel 7T-based ripple carry adder (RCA) significantly reduces area overhead. The proposed 16Kb macro computes 64 parallel products per clock cycle and achieves 2ˆ higher energy efficiency over recent SoTA works at 65nm CMOS. The macro is validated at 250MHz and demonstrates classification accuracy of 98.7%, 98.8% for 1A4W precision, and 99.1%, 97.8% for 4A4W precision on LeNet-5 using MNIST and A-Z datasets respectively.