Architecture and CAD for emerging technologies

Abstract

FPGAs started becoming popular in the last two decades of the 20th century, as they were more flexible than Application Specific Integrated Circuits (ASICs) and faster than General Purpose Processors (GPPs). Serving as a middle ground between them, FPGAs had the ability to adapt to application requirements and hence started finding uses in multitude of fields due to their low design turn-over time. However, with transistors scaling (as per Moore’s Law) and power scaling (as per Dennard’s scaling) hitting a cost and power-density wall, respectively, it is imperative to have a fresh perspective. As the cost-per-transistor is increasing with sub 10nm CMOS technology nodes, we shed some light on a system-level technique i.e. Partial Reconfiguration and evaluate the suitability of novel ‘more-than-Moore’ devices like reconfigurable FETs (RFETs), both of which help to circumvent the cost and power issues. We survey the emerging approaches of FPGA logic cell design with novel devices like Si/Ge-nanowire transistors, CNTFETs, memristors and spintronics along with proposed non-LUT architectures like fine-grained clusters and And-Inverter Cones (AICs). We also do a preliminary survey of novel devices with open-source compact models and carry on the most promising one to propose a new logic cell design 4M and 4M-scaled along and implement it with conventional crossbars. We also evaluate the suitability of RFET-based NAND-NOR design for the ‘cone’ architecture and show lesser delay-variance between the configurations than the state-of-the-art. We also delve into the security aspects of RFETs and show the possible attack and defence mechanisms.