HLS Trojan Tampering Attack of IP Designs for Power Drainage using Timer-Sensitive Trojan Trigger based Automated Logic-Transformation

Abstract

Hardware intellectual property (IP) designs used in the system-on-chip of electronics systems are designed using High-level synthesis (HLS). However, HLS design phases exposes security vulnerabilities that an attacker (rogue HLS tool developer) can exploit to covertly insert backdoor hardware Trojan (HT) in order to achieve various Trojan payloads. This paper introduces a new type of HLS-aided HT vector for inducing tampering attack on IP designs called ‘Timer-Sensitive Trojan trigger based automated logic-Transformation (TST-HT)’ that can induce significant power drainage in IP designs. The proposed HLS-aided TST-HT can be inserted covertly during the datapath design stage and triggered under attacker pre-defined timer-sensitive rare condition which makes it elusive by nature. © 2009-2012 IEEE.