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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/17894
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dc.contributor.authorKumar, Mukeshen_US
dc.date.accessioned2026-02-20T13:23:48Z-
dc.date.available2026-02-20T13:23:48Z-
dc.date.issued2025-
dc.identifier.citationZaidour, I., Rizkalla, M. E., Ytterdal, T. A., Lee, J. J., & Kumar, M. (2025). Memristor-Based Hardware Architecture for Edge Detection. Proceedings of the IEEE National Aerospace Electronics Conference, NAECON. https://doi.org/10.1109/NAECON65708.2025.11235388en_US
dc.identifier.isbn9781509034413-
dc.identifier.isbn9781467375658-
dc.identifier.isbn9781538665572-
dc.identifier.isbn9781538632000-
dc.identifier.isbn9781728114163-
dc.identifier.isbn9798350338782-
dc.identifier.isbn9781665448598-
dc.identifier.isbn9798350367621-
dc.identifier.isbn9798331538132-
dc.identifier.issn0547-3578-
dc.identifier.otherEID(2-s2.0-105029434683)-
dc.identifier.urihttps://dx.doi.org/10.1109/NAECON65708.2025.11235388-
dc.identifier.urihttps://dspace.iiti.ac.in:8080/jspui/handle/123456789/17894-
dc.description.abstractThis paper introduces a memristor-based edge detection architecture designed to enhance hardware efficiency for AI and real-time applications. Memristors are utilized for their compact size, low power requirements, and ability to integrate memory and computation within a single device. The proposed design reduces circuit complexity and demonstrates effective performance in targeted test cases compared to traditional analog edge detection circuits. Implementing the Sobel filter with memristors enables efficient, parallel edge detection while minimizing power usage. Simulation results confirm the approach's viabilityen_US
dc.description.abstracthowever, current evaluations are limited to specific scenarios. Future work will focus on extending validation across more diverse conditions. © 2025 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceProceedings of the IEEE National Aerospace Electronics Conference, NAECONen_US
dc.titleMemristor-Based Hardware Architecture for Edge Detectionen_US
dc.typeConference Paperen_US
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