SRAM-based RO PUF architecture for edge devices

Abstract

In recent years, the rapid expansion of connected systems, edge computing platforms, and Internet of Things (IoT) devices has created a strong demand for lightweight and energy-efficient hardware security solutions. Traditional security techniques rely heavily on software-based cryptography and externally stored secret keys, which are increasingly vulnerable to physical attacks, cloning, and reverse engineering. Resource-constrained devices often cannot afford the computational and storage overhead associated with conventional cryptographic schemes. As a result, modern security architectures must rely on low-power, low-area, and tamper-resistant hardware primitives that can provide identity, authentication, and key generation at the silicon level. With the increasing proliferation of connected devices and edge computing platforms, ensuring hardware-level security has become a critical requirement. Physical, Unclonable Functions (PUFs) offer a lightweight and reliable approach for device authentication and secure key generation by exploiting inherent manufacturing variations in integrated circuits. This thesis presents the design and analysis of reconfigurable and memory-centric PUF architectures that integrate oscillator-based entropy generation with compute-in-memory principles to enhance security and reliability.