Mitigating Charge Injection Bottlenecks via Dual-Doped Source/Drain for High-Speed Low-Voltage Capacitorless Dynamic Memory

Abstract

This work demonstrates the feasibility of thermionic injection-based program and erase operations for enabling a low-voltage, high-speed capacitorless dynamic random access memory (DRAM) via a dual-doped (DD) source/drain (S/D) transistor. The proposed capacitorless DRAM achieves a low latency (<0.5 ns), low energy consumption (~1.4 fJ), excellent retention (~200 ms at 85 °C) at a logic-compatible supply voltage of ±0.6 V while maintaining functionality at elevated temperatures (~5 ms at 125 °C). Results highlight the usefulness of DD-S/D engineering for high-speed, energy-efficient embedded cache and edge computing. © 1963-2012 IEEE.