A Novel 4-Bit CMOS Based Full Adder for Low-Power IoT and Edge Computing Applications

Abstract

This work introduces a new 4-bit CMOS adder design that uses only 31 transistors, a significant reduction from 75 transistors needed for traditional static CMOS implementations. Through careful transistor sizing and circuit-level improvements, the suggested adder greatly reduces silicon area and power consumption while preserving competitive speed and signal integrity by utilizing an optimized pass-transistor logic topology. We also show that this little 4-bit adder can be expanded to build effective compressor circuits, which are essential for cutting down on adder tree stages in multi-operand addition processes. Particularly well-suited for incorporation into Compute-in-Memory (CIM) frameworks, the suggested compressor architecture allows for in-situ arithmetic processing, which significantly minimizes data travel and boosts computational throughput. This work's average power consumption of 138.2 μW and propagation delays are 0.666 ns for the sum output (S), 0.0302 ns for carry-out C1, and 0.03227 ns for carry-out C2. This design pushes the boundaries of arithmetic circuit efficiency in cutting-edge CMOS technologies and provides a convincing solution for next-generation low-power, area-constrained system-on-chip (SoC) scenarios. © 2025 IEEE.