Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/18215
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dc.contributor.authorKumar, Sonuen_US
dc.contributor.authorNair, Arjun S.en_US
dc.contributor.authorChaudhary, Bhawnaen_US
dc.contributor.authorLokhande, Mukulen_US
dc.contributor.authorVishvakarma, Santosh Kumaren_US
dc.date.accessioned2026-05-14T12:28:17Z-
dc.date.available2026-05-14T12:28:17Z-
dc.date.issued2026-
dc.identifier.citationKumar, S., Nair, A. S., Chaudhary, B., Lokhande, M., & Vishvakarma, S. K. (2026). ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. https://doi.org/10.1109/TVLSI.2026.3680055en_US
dc.identifier.issn1063-8210-
dc.identifier.otherEID(2-s2.0-105035640328)-
dc.identifier.urihttps://dx.doi.org/10.1109/TVLSI.2026.3680055-
dc.identifier.urihttps://dspace.iiti.ac.in:8080/jspui/handle/123456789/18215-
dc.description.abstractThis brief presents a cortical neural pool (CNP) architecture incorporating a high-speed, resource-efficient CORDIC-based Hodgkin–Huxley (RCHH) neuron. The design employs modular CORDIC stages with a latency–area tradeoff and introduces a constraint-aware modular parallelism (CAMP) scheme with precision and stability handling. The FPGA implementation achieves 24.5% lower LUT utilization and 35.2% faster execution than prior designs while reducing normalized root-mean-square error (NRMSE) by 70%. The CNP engine provides 2.85× higher throughput (12.69 GOPS) than a functionally equivalent CORDIC-based DNN accelerator with only 0.35% accuracy degradation on MNIST. These results demonstrate a biologically accurate, resource-efficient cortical neural acceleration engine (NCE) that employs modular CORDIC stages with a latency–area tradeoff, making it suitable for resource-constrained edge-AI systems. The implementation is publicly available at https://github.com/mukullokhande99/CNP_RCHH © 1993-2012 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceIEEE Transactions on Very Large Scale Integration (VLSI) Systemsen_US
dc.titleReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engineen_US
dc.typeJournal Articleen_US
dc.rights.licenseAll Open Access-
dc.rights.licenseGreen Open Access-
Appears in Collections:Centre for Advanced Electronics (CAE)
Department of Electrical Engineering

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