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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kumar, Sonu | en_US |
| dc.contributor.author | Nair, Arjun S. | en_US |
| dc.contributor.author | Chaudhary, Bhawna | en_US |
| dc.contributor.author | Lokhande, Mukul | en_US |
| dc.contributor.author | Vishvakarma, Santosh Kumar | en_US |
| dc.date.accessioned | 2026-05-14T12:28:17Z | - |
| dc.date.available | 2026-05-14T12:28:17Z | - |
| dc.date.issued | 2026 | - |
| dc.identifier.citation | Kumar, S., Nair, A. S., Chaudhary, B., Lokhande, M., & Vishvakarma, S. K. (2026). ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. https://doi.org/10.1109/TVLSI.2026.3680055 | en_US |
| dc.identifier.issn | 1063-8210 | - |
| dc.identifier.other | EID(2-s2.0-105035640328) | - |
| dc.identifier.uri | https://dx.doi.org/10.1109/TVLSI.2026.3680055 | - |
| dc.identifier.uri | https://dspace.iiti.ac.in:8080/jspui/handle/123456789/18215 | - |
| dc.description.abstract | This brief presents a cortical neural pool (CNP) architecture incorporating a high-speed, resource-efficient CORDIC-based Hodgkin–Huxley (RCHH) neuron. The design employs modular CORDIC stages with a latency–area tradeoff and introduces a constraint-aware modular parallelism (CAMP) scheme with precision and stability handling. The FPGA implementation achieves 24.5% lower LUT utilization and 35.2% faster execution than prior designs while reducing normalized root-mean-square error (NRMSE) by 70%. The CNP engine provides 2.85× higher throughput (12.69 GOPS) than a functionally equivalent CORDIC-based DNN accelerator with only 0.35% accuracy degradation on MNIST. These results demonstrate a biologically accurate, resource-efficient cortical neural acceleration engine (NCE) that employs modular CORDIC stages with a latency–area tradeoff, making it suitable for resource-constrained edge-AI systems. The implementation is publicly available at https://github.com/mukullokhande99/CNP_RCHH © 1993-2012 IEEE. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
| dc.source | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | en_US |
| dc.title | ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine | en_US |
| dc.type | Journal Article | en_US |
| dc.rights.license | All Open Access | - |
| dc.rights.license | Green Open Access | - |
| Appears in Collections: | Centre for Advanced Electronics (CAE) Department of Electrical Engineering | |
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