Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/18277
Title: SHiELD: Functional Obfuscation of DSP Cores Using HLS Based One-Way Random Function and Reconfigurable Composite Switching Obfuscation Cells
Authors: Sengupta, Anirban
Anshul, Aditya
Bhui, Nabendu
Issue Date: 2026
Publisher: Association for Computing Machinery
Citation: Sengupta, A., Anshul, A., & Bhui, N. (2026). SHiELD: Functional Obfuscation of DSP Cores Using HLS Based One-Way Random Function and Reconfigurable Composite Switching Obfuscation Cells. ACM Transactions on Embedded Computing Systems, 25(2). https://doi.org/10.1145/3793677
Abstract: Successful reverse engineering (RE) of digital signal processing (DSP) integrated circuits (ICs) by an attacker provides him/her a chance to pirate the DSP-based intellectual property (IP) and insert malicious logic. It is thus central to devise low-cost sturdy functional obfuscation techniques for DSP cores that hinders RE attempt (or increases attackers effort manifold). There has been meager effort on devising robust high-level synthesis (HLS) based functional obfuscation methodology that is low-cost/power. This paper presents a novel <ani:underline>S</ani:underline>ecure <ani:underline>Hi</ani:underline>gh-Level synthesis based functional obfuscation methodology for <ani:underline>E</ani:underline>nhanced security of <ani:underline>D</ani:underline>SP cores called “SHiELD” that is driven through HLS based one-way random (OWR) function and reconfigurable composite switching obfuscation (CSO) cells, integrated with design space exploration process. The proposed approach offers security against different relevant attacks and in overall effectively thwarts RE attempt with the aid of proposed multi-key bit CSO cells, and custom OWR function. The results of the proposed approach in comparison with prior approaches yielded several magnitudes of higher security (robust obfuscation strength and lower probability of key retrieval) upto ∼10154 (for FIR-2 benchmark calculated using Equation (1)), lower power (of ∼10.6%) and reduction in design cost (of 0.91%). © 2026 Copyright held by the owner/author(s).
URI: https://dx.doi.org/10.1145/3793677
https://dspace.iiti.ac.in:8080/jspui/handle/123456789/18277
ISSN: 1539-9087
Type of Material: Journal Article
Appears in Collections:Department of Computer Science and Engineering

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