REFLEX-PIM: A Resource-Efficient and Flexible Trans-Precision Digital Processing-in-Memory SRAM Macro for AI Workloads

Abstract

This work presents REFLEX-PIM, a resourceefficient and flexible trans-precision digital Processing-in-Memory (PIM) SRAM macro that integrates posit-computations and floating-point non-linear activation function (NAF) within the macro. This work reduces the overhead associated with the pre/-post-processing pipeline in prior works with the SIMD-shared hardware approach and performance-enhanced SRAM Unified PIM (UPIM) engine. This work utilises a shared datapath for the SRAM UPIM engine, Shift-OR-based regime handling and a novel transistor-reduced compressor tree (TRCT) for 67.7% area and 79.5% power savings with processing-in-hardware and 65.3% transistor reduction in accumulation. The proposed 16Kb PIM macro delivers 3.38 TFLOPS throughput (Posit-4) at 37.6 TFLOPS/W energy efficiency and 0.4 TFLOPS/mm2 compute density at 65 nm CMOS process. The detailed application-level evaluations showcase comparable accuracy (within 1-2%) with baseline and prior works, while shrinking model size significantly up to 5.6×. REFLEX-PIM shows 4.34× higher energy efficiency and 1.9× higher compute density, compared to recent SoTA macros. This assessment marks REFLEX-PIM as a potential PIM solution for next-generation XR SoC systems. © 2025 IEEE.