Comprehensive Noise Modeling and Analysis for SRAM, RRAM, and MRAM for Analog In-Memory Computing

Abstract

Analog In-Memory Computing (AIMC) architectures, leveraging traditional and emerging memory technologies such as SRAM, RRAM, and MRAM, offer promising energy-efficient solutions for neural network acceleration. Despite their advantages, AIMC systems are highly susceptible to noise from both intrinsic device mechanisms and peripheral circuits, which can significantly degrade computational accuracy and reliability. This paper presents a comprehensive, technology-aware noise modeling framework that captures device-level noise including thermal noise, random telegraph noise (RTN), conductance variability, retention degradation, and switching failures as well as peripheral circuit noise such as ADC/DAC quantization errors, comparator offsets, clock jitter, and interconnect parasitics. Correlated noise due to shared bias lines and wordline drivers is also incorporated. Detailed stochastic noise models are developed for SRAM, RRAM, and MRAM and implemented in MATLAB, with comparisons against simplified Gaussian noise baselines. Simulation results reveal the distinct noise characteristics of each memory type and highlight the limitations of idealized noise assumptions, providing critical insights for AIMC design and noise mitigation strategies. © 2026 IEEE.