Enhancing Edge AI: A Digital Compute-In-Memory SRAM Macro for Vector Matrix Multiplication

Abstract

This article presents a 16-Kb Digital Compute-In-Memory (DCIM) SRAM Macro capable of performing vector matrix multiplication (VMM) between a 64-D input vector and a 64x64 weight matrix, with numbers being in 4-bit unsigned integer format. The proposed DCIM macro employs a custom-designed 10-transistor (T) NOR bitcell and 18-transistor (T) Full Adder as the core components of the architecture. It has been implemented using a stanadard TSMC 65-nm CMOS technology node. The proposed macro has the potential to be used as a core component of a hardware accelerator for efficient processing of neural networks. It supports 4-bit/1-bit activations and 4-bit weights. The simulation results show that the design achieves a throughput of 1484.05 GOPS (normalized to 4b/4b), 5936.23 GOPS/W (normalized to 4b/1b), and a power efficiency of 0.405W (normalized to 4b/4b). An estimated accuracy of 86.2% has been obtained for the LeNet-5 CNN model (quantized to 4-bit weights and inputs to model our macro) trained and tested on the MNIST dataset. © 2025 IEEE.