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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Chaudhari, Tejas | en_US |
| dc.contributor.author | Akarsh, Jayanth | en_US |
| dc.contributor.author | Dewangan, Tanushree | en_US |
| dc.contributor.author | Lokhande, Mukul | en_US |
| dc.contributor.author | Vishvakarma, Santosh Kumar | en_US |
| dc.date.accessioned | 2026-05-14T12:28:27Z | - |
| dc.date.available | 2026-05-14T12:28:27Z | - |
| dc.date.issued | 2026 | - |
| dc.identifier.citation | Chaudhari, T., Akarsh, Dewangan, T., Lokhande, M., & Vishvakarma, S. K. (2026). XR-NPE: High-Throughput Mixed-Precision SIMD Neural Processing Engine for Extended Reality Perception Workloads. Proceedings - 2026 39th International Conference on VLSI Design and 25th International Conference on Embedded Systems, VLSID 2026, 37–42. https://doi.org/10.1109/VLSID68508.2026.00021 | en_US |
| dc.identifier.isbn | 979-833159040-6 | - |
| dc.identifier.other | EID(2-s2.0-105036822712) | - |
| dc.identifier.uri | https://dx.doi.org/10.1109/VLSID68508.2026.00021 | - |
| dc.identifier.uri | https://dspace.iiti.ac.in:8080/jspui/handle/123456789/18356 | - |
| dc.description.abstract | This work proposes XR-NPE, a high-throughput Mixed-precision SIMD Neural Processing Engine, designed for extended reality (XR) perception workloads like visual inertial odometry (VIO), object classification, and eye gaze extraction. XR-NPE is the first to support FP4, Posit (4,1), Posit (8,0), and Posit (16,1) formats, with a layer-adaptive hybrid-algorithmic implementation that supports ultra-low bit precision to significantly reduce memory bandwidth requirements. This is accompanied by quantisation-aware training to minimise accuracy loss. The proposed Reconfigurable Mantissa Multiplication and Exponent Processing Circuitry (RMMEC) reduces dark silicon in the SIMD MAC compute engine, assisted by selective power gating to reduce energy consumption, resulting in a 2.85 × improvement in arithmetic intensity. XR-NPE achieves a maximum operating frequency of 1.72 GHz, area 0.016 ~mm2, and arithmetic intensity 14 pJ at CMOS 28 nm, reducing 42% area, 38% power compared to the best of state-of-the-art MAC approaches. The proposed XR-NPE-based AXI-enabled Matrix-multiplication co-processor consumes 1.4 × fewer LUTs, 1.77 × fewer FFs, and provides 1.2 × better energy efficiency compared to SoTA accelerators on VCU129. The proposed co-processor provides 23% better energy efficiency and 4% better compute density for VIO workloads. XR-NPE establishes itself as a scalable, precision-adaptive compute engine for future resource-constrained XR devices. The complete set for codes https://github.com/mukullokhande99/XRNPE for results reproducibility are released publicly, enabling designers and researchers to readily adopt and build upon them. © 2026 IEEE. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
| dc.source | Proceedings - 2026 39th International Conference on VLSI Design and 25th International Conference on Embedded Systems, VLSID 2026 | en_US |
| dc.title | XR-NPE: High-Throughput Mixed-Precision SIMD Neural Processing Engine for Extended Reality Perception Workloads | en_US |
| dc.type | Conference Paper | en_US |
| Appears in Collections: | Department of Electrical Engineering | |
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